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    4,586 verilog vhdl 份搜到的工作,货币单位为 USD

    I need a design on verilog hdl that implements double MIPS at the same time

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    The detailed paper of the project is attached below. The skills required for the same are MATLAB, Xilinix, Verilog.

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    Implementar, simular FFT en entorno aldec , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desarrollar código VHDL y detallar minuciosamente paso a paso, tomar captures y realizar documento de word detallando cada paso la oferta es de 90 usdt. Se cuenta con la tarjeta en físico por lo cual se ofrece conexión remota

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    Debuging verilog 15 小时 left

    Debuging verilog

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    • Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env. • Understanding of verification tools like Simulator, Synthesis etc. • Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL • Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc. • Excellent written and verbal interpersonal skills • Self-motivated and great teammate

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    I need a design on verilog hdl that implements double MIPS at the same time

    $25 / hr (Avg Bid)
    $25 / hr 平均报价
    11 个竞标

    السلام عليكم ورحمة الله وبركاته واسعد الله اوقاتك بكل خير عندي واجب ومحتاج مساعدتك اذا وقتك يسمح. انشاء بروجكت بال verilog بحيث يقرأ محتويات ال ROM ويخرج المحتوى على LEDs

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    Project for Ahmed M. 已经结束 left

    Hi Ahmed M., I need your help on single-port ROM verilog project. Please have a look to the attached file and let me know. Thanks

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    VHDL test procedure and test bench implementation

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    VHDL designer -- 2 已经结束 left

    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

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    VHDL designer 已经结束 left

    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

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    Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing

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    -Write a VHDL file for an 8-bit counter with active-LOW asynchronous clear, active-HIGH synchronous load, active-HIGH count enable, and a directional input that makes the circuit count up when DIRECTION = 1 and down when DIRECTION = 0. - Write a set of simulation criteria that verifies the operation of the counter. The simulation must contain one complete cycle of the counter and test all functions. It must show that the synchronous load really is synchronous and that the clear has precedence over load, which in turn has precedence over count enable. -Write a VHDL file for a two-digit BCD counter with active-LOW asynchronous clear, active- HIGH synchronous load, and an active-HIGH count enable. -The counter must count up from 00 to 09, then 10 to 19, and so on until it reache...

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    Hi I need RISC V RTL code using Verilog.

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    Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

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    ticketing machine system 已经结束 left

    ticketing machine system via Verilog codes using quarters ll

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    I will love to chat with you about my project. Please let me know when you can https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details

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    Project for Damian L. 已经结束 left

    I will love to chat with you about my project. Please let me know when you can https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details

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    Project for Loganathan N. 已经结束 left

    I have a project i want to talk to you about https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details Please let me know when you have time to chat

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    Verilog, SV & UVM Trainer 已经结束 left

    We are looking for a trainer, who teach online Verilog, SV & UVM to students

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    - write Verilog code for steganography algorithm so that I can be implemented on FPGA - using Verilog Xilinx ise have to write module code & test bench where it can be implemented on Fpga

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    I have a MATLAB code and want this to be converted to HDL code using HDL Coder feature available in MATLAB. I have attached the error what i am getting currently

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    These are the blocks. TO BE CODED in Verilog or system verilog. REGISTER BLOCK IS APB COMPLIANT. A USER SHOULD BE ABLE TO READ AND AND WRITE THE REGISTERS IN THE REGISTER BLOCK USING APB PROTOCOL. THE REGISTERS ARE THE AXI READ AND WRITE DATA CHANNEL SIGNALS.EX- ARADDR, ARBURST, ARPROT, ARSIZE, ALEN etc.(all the read channel registers). These registers should be given as inputs to the READ TRANSACTION GENERATOR BLOCK. This block should be able to generate the AXI legal transactions without using handshake signals. Transactions should be stored in FIFO and later BFM pops up the transactions and gives it to the AXI bus. BFM acts like AXI master.

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    I am looking for an FPGA (Verilog) expert who can help me to troubleshoot and implement the EdDSA algorithm in Xilinx Vivado Design Suite. The Vivado project file is available in the attachments and several modules of the project are already completed. Looking for an expert who can do it in 3 to 4 days. Further information will be provided in the discussion.

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    Verilog ALU 已经结束 left

    I will provide you the code and screenshots of the results.

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    ALU in Verilog 已经结束 left

    I will provide you verilog code and screenshots of results.

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    ASIC designer -- 3 已经结束 left

    One of the most prestigious companies in the field of ASIC Design is looking for a talented Digital ASIC Designer, especially in the field of artificial intelligence algorithms. Required capabilities and skills are as follows: *Holding a bachelor or master's degree in electronics *Having adequate knowledge of digital design *Proficient in digital flow *Familiar with Verilog, VHDL languages *Experience with EDA tools from Cadence, Mentor, and Synopsys(SOC design & encounter) *Experienced in Transform specification from RTL to silicon CMOS circuitry *Ability to analyze designed circuits and optimizing them *Proficiency in problem solving *Ability to interact and collaborate with R&D colleagues *Experience with tapeout is preferred.

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    Verilog multiplier 已经结束 left

    I will provide you the verilog code for Montgomery n-bit radix 8 multiplier with the screenshots of results and stimulation.

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    Required the verilog implementation of N bit Montgomery Radix 8 bit multiplier and for addition use the CLA adder.

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    Using Pynq Z2 FPGA to connect a camera (OV7670 - CMOS Sensor), and then display the video on a monitor through HDMI output. The Project is built using VHDL language and IP blocks. The purpose of this it's to build also nurual network to recognize a face/person so the camera can follow the object using servo motor.

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    FEC RS(198, 194) 已经结束 left

    Verilog FPGA Code implementation of FEC RS(198, 194) decoder.

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    FEC RS(198,194) Verilog 已经结束 left

    I want go get help to implement FEC RS(198, 194)

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    vhdl expert 已经结束 left

    I want Signal processing and VHDL(Quartus Application) expert.

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    5G RAN FPGA Design 已经结束 left

    We have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · To...

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    I want you to desgin an IC chip description document. I need you to understand the verilog design and create some design descriotions, describing its fucntions in detail. The chip design has 3 main blocks ADC, PMU and sensors. These 3 blocks contain the most important functions of this chip. Please bid if you are experienced in wrting technical design documents for chip desing in detail. Thanks!

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    A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erro...controle de erros. Isto pode ser feito através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa quando um...

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    I have the code for I2C slave. I want help in writing the verilog code for I2C Master testbench to communicate with the given slave. It can send a few i2C write and read commands (with address, data, etc). I have attached the code for I2C slave alonside for your reference.

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    1.VHDL code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.

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    Your job is to write verilog code for i2c communication and interface it with a processor. Take data from the slave through the accelerator and store it in a memory. Make the processor read the data from that memory and give its response. Now write that response data back to the slave.

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    SOC Verification 已经结束 left

    ...ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption. 3. Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification. 4. Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage. 5. Experience in Verification methodologies(UVM, OVM and eRM). language simulation (Verilog-AMS, SystemVerilog). 7. Experience in Mentor, Cadence and Synopsys simulators. 8. Build automated Test bench and regression environments from a scratch. Should be able to write a test plan and generate test cases 9. Regression management and Verification Sign-off based o...

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    I need Verilog code for Energy-Efficient Logarithmic Square Rooter. It should be done within 1-2 days maximum.

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    I am looking to develop a Verification Code using System Verilog for USB 2.0 Protocol and also I want a verification plan for that . Kindly note that I want Complete TB code for all the components in Environment and also Test and Top instances as well . For any query/ or clarity ping me.

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    A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.

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    We need a project done in Morse code encoder and decoder in VHDL. Our project contains 2 parts a transmitter and receiver. The transmitter part receives the text(ASCII) from the PC(user) via UART receiver and transmits the text to morse code encoder(converts text to morse code). The morse code pattern then is sent to an led. Dot(.) corresponds to LED on and dash(-) LED off. The receiver part has a photo diode which reads the blinking of the led(morse code) and data is transmits to Morse decoder where it is converted back to ASCII. The converted ASCII is then transmitted to end user PC for display. We have already designed the top level top level block diagram. we now need the source codes(entity and architecture) for the blocks and test benches for all blocks for simulation...

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    STM32 toolchain and also vhdl design with report describing the procedures

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    quartus and modulsim 已经结束 left

    i want some vhdl coding simulating with test bench on modulsim and a report

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    FPGA Project 已经结束 left

    I need to do simple FPGA project on Boolean Board (Real Digital). For example Tic Tac Toe game. software should be Vivado and programming should be done in Verilog.

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    This project requires basic knowledge of digital electronics and VHDL coding.

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    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $20 - $67
    加封
    $20 - $67
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    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $7 - $40
    加封
    $7 - $40
    5 个竞标