Verilog / VHDL 工作与竞赛

Verilog是一种用于半导体和电子设计领域的描述语言,也常用于模拟和模数混合电路中。VHDL则是一种用于电子设计自动化和集成电路的硬件描述语言。如果您的业务涉及Verilog / VHDL,您可以雇佣一些自由职业者完成部分作业。现在就发布您的Verilog/VHDL项目需求,与中意的自由职业者取得联系吧。
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项目/竞赛 描述 竞标数/参赛作品数 技能 已开始 结束 价格(CNY)
Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 7 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Oct 17, 2017 今天6天 22时 ¥898
Matlab power system Simulation using Simulink My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 8 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Oct 17, 2017 今天6天 20时 ¥1088
电機工程, 电子, LabVIEW, 微控制器, Verilog / VHDL Oct 16, 2017 今天6天 14时
netlist construction in EE using C++ refactor the sample code by using the c++ 7 C 编程, Verilog / VHDL, C# 编程, 电機工程, C++编程 Oct 16, 2017 今天6天 3时 ¥867
project for Ahmed M -- 2 - 16/10/2017 12:09 EDT I believe you must do this project. 2 Verilog / VHDL Oct 16, 2017 今天6天 2时 ¥841
project for Ahmed M I believe you must do this project. 1 Verilog / VHDL Oct 16, 2017 今天6天 2时 ¥1026
verilog project want verilog code on fpga i want soon 2 工程, Verilog / VHDL, 软件构架, LabVIEW, FPGA Oct 16, 2017 今天6天 1时 ¥53
50 usd zynq verilog C project 50 usd Initial zynq verilog C project 7 C 编程, Verilog / VHDL, 微控制器, C++编程, FPGA Oct 16, 2017 Oct 16, 20175天 19时 ¥305
ASIC Designs and Development Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... 5 工程, 电子, Verilog / VHDL, 电機工程, 印制板布局 Oct 16, 2017 Oct 16, 20175天 19时 ¥113
veriloghdl code for calculation area THis must implement on quartus( altera FPGA cyclone IV) 3 C 编程, Verilog / VHDL, 微控制器, C++编程, FPGA Oct 16, 2017 Oct 16, 20175天 18时 ¥470
making verlog hdl code calculataion area in black and white image on fpga ( cyclone IV) 7 C 编程, Verilog / VHDL, 微控制器, 电機工程, C++编程 Oct 16, 2017 Oct 16, 20175天 15时 ¥821
VHDL Coursework help in VHDL codes ,, everything will be explained later 11 工程, 电子, Verilog / VHDL, 电機工程 Oct 15, 2017 Oct 15, 20175天 6时 ¥369
fpga software I want to read programmes in FPGA chips 17 C 编程, Verilog / VHDL, 软件构架, FPGA Oct 15, 2017 Oct 15, 20175天 1时 ¥2734
creation of hardware module using verilog which will be able to communicate with the memory of the processor using Verilog which will be able to communicate with the memory of the processor 3 Verilog / VHDL Oct 14, 2017 Oct 14, 20174天 ¥417
simple verilog hdl code calculate each area in black and white image 10 C 编程, 工程, Verilog / VHDL, 微控制器, FPGA Oct 13, 2017 Oct 13, 20173天 13时 ¥271
Simple Verilog Project Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. 7 工程, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Oct 13, 2017 Oct 13, 20173天 6时 ¥132
Color space conversions and FPGA's 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. 8 工程, Verilog / VHDL, 电機工程, FPGA Oct 13, 2017 Oct 13, 20172天 20时 ¥457
Build software Looking for expert in FPGA and verilog 18 C 编程, Verilog / VHDL, 软件构架, C++编程, FPGA Oct 12, 2017 Oct 12, 20171天 15时 ¥3178
Statcom in simulink Power electronics expert -- 3 Statcom in simulink Power electronics expert needed 12 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Oct 11, 2017 Oct 11, 201721时 14分 ¥1724
Statcom in simulink Power electronics expert -- 2 Statcom in simulink Power electronics expert needed 9 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Oct 11, 2017 Oct 11, 201718时 19分 ¥1087
Want to develop robotic program and test the same with simulation to check feasibility of and automation idea Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... 5 矩阵及数学软件, Verilog / VHDL, 软件构架, 软件开发, 编程 Oct 11, 2017 Oct 11, 201717时 32分 ¥30979
Convert a code from Aptech Gauss language into Matlab with Parallel processing.....!!!! I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. 5 矩阵及数学软件, Verilog / VHDL, 软件构架, CUDA, 软件开发 Oct 11, 2017 Oct 11, 201716时 44分 ¥799
VLSI PROJECTS FIND THE ATTACHED IEEE [链接已删除,请登录查看] REQUIREMENTS 4 Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) Oct 11, 2017 Oct 11, 201715时 43分 ¥568
Statcom in simulink Power electronics expert Statcom in simulink Power electronics expert needed 9 电子, 矩阵及数学软件, Verilog / VHDL, FPGA Oct 11, 2017 Oct 11, 201715时 3分 ¥753
Convert a code from Aptech Gauss language into Matlab with Parallel processing. I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. 3 矩阵及数学软件, Verilog / VHDL, 软件构架, CUDA, 软件开发 Oct 10, 2017 Oct 10, 201713时 49分 ¥1012
Develop, Test and Implement it in software environment and simulate the circuit functionality - open to bidding We need to develop a digital multiplier circuit and we need to test the circuit design, Implement it in software environment and simulate the circuit functionality. This is going to be part of a bigger project (ARM IP Core, DSP CPU) and we may need to compare the circuit functionality with some other recommended multiplier in terms of speed and foot print. 7 电子, Verilog / VHDL, 电機工程, 数字设计, 电路设计 Oct 10, 2017 Oct 10, 201710时 12分 ¥706
Prelab Write VHDL code 7 Verilog / VHDL Oct 10, 2017 Oct 10, 20175时 1分 ¥179
dimensionality reduction using PCA we will consider use of PCA for simple dimensionality reduction, i.e., determining the signal subspace when there are more observations than the underlying latent variables—signals. The main assumption here is that both the noise and signals are independent and identically distributed Gaussians, however the the signals are correlated among themselves while the noise components are not, ... 14 矩阵及数学软件, Verilog / VHDL, 有限元分析, CUDA, FPGA Oct 10, 2017 Oct 10, 20174时 48分 ¥2701
ZYNQ c/ verilog project(s) There is a Zynq C/ Verilog project involving BRAM and data structures , to be done. We will start with a 50 usd small project, on successful completion we will move into larger budget projects( a few hundred USD ones) .PM me to talk the details. 11 C 编程, Verilog / VHDL Oct 10, 2017 Oct 10, 2017已经结束 ¥543
Altera DE115 - Audio signal processing Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers 9 Verilog / VHDL, 微控制器, 嵌入式软件, 汇编, FPGA Oct 10, 2017 Oct 10, 2017已经结束 ¥1494
Audio Signal Processing AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... 7 Verilog / VHDL, 微控制器, 电機工程, 嵌入式软件, FPGA Oct 10, 2017 Oct 10, 2017已经结束 ¥3367
Sequence Diagram There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [链接已删除,请登录查看]() b. Call [链接已删除,请登录查看](Account) c. Call [链接已删除,请登录查看]() d. [链接已删除,请登录查看]() calls [链接已删除,请登录查看](amount) which makes the payment e. Call [链接已删除,请登录查看](Order) which saves the order f. Call [链接已删除,请登录查看]() whic... 6 Verilog / VHDL, 软件构架, PLC 与 SCADA, 有限元分析, 工程制图 Oct 10, 2017 Oct 10, 2017已经结束 ¥245
Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [链接已删除,请登录查看] 22 Excel, 矩阵及数学软件, Verilog / VHDL, 软件构架, 软件开发 Oct 7, 2017 Oct 7, 2017已经结束 ¥144
UML/MARTE modeling I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). 1 Verilog / VHDL, UML 设计, 有限元分析, SAS, 计算机图形辅助三维交互式应用 Oct 7, 2017 Oct 7, 2017已经结束 ¥3883
Stack Automata C++ All requirements in PDF. A Stack Automata for validate a string 7 Verilog / VHDL, 有限元分析, 序言, C++编程, Haskell Oct 7, 2017 Oct 7, 2017已经结束 ¥311
matlab report making 10 pages minimum hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote 10 矩阵及数学软件, Verilog / VHDL, LaTeX, 数学, 物理 Oct 7, 2017 Oct 7, 2017已经结束 ¥318
Matlab Write a Function for Forward Kinematics of the RPR Robot Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... 16 矩阵及数学软件, Verilog / VHDL, 软件构架, 有限元分析, 软件开发 Oct 7, 2017 Oct 7, 2017已经结束 ¥251
String compare algorithm need an algorithm that would compare two long strings delimited by | 3 矩阵及数学软件, Verilog / VHDL, 算法, CUDA, 机器学习 Oct 7, 2017 Oct 7, 2017已经结束 ¥12975
Cryptoanalysis - Cryptograpgy - C programming I am looking for someone to write me a code in c that will test the cryptographic strength of the passwords. I can share more specific instructions and dummy passwords. I need a simple program. 9 C 编程, Verilog / VHDL, 软件构架, 序言, C++编程 Oct 6, 2017 Oct 6, 2017已经结束 ¥456
MSF and DCF receiver everything will me explained later 5 工程, 电子, Verilog / VHDL, 电機工程, 二进制分析 Oct 6, 2017 Oct 6, 2017已经结束 ¥303
Embedded Control System Design It is a project on Embedded Control System Design. I will give the details later. 12 C 编程, Verilog / VHDL Oct 6, 2017 Oct 6, 2017已经结束 ¥291
ABAQUS Model (CFRP Beam) I need to make the results of this ABAQUS model converge with the experimental data curve (shown in the Excel sheet: Load vs Deflection). The current results shows a much higher yield and peak loading compared to the experimental data. The model files are attached to this project. 13 Verilog / VHDL, 有限元分析, 计算机图形, 工业工程, 计算机图形辅助三维交互式应用 Oct 5, 2017 Oct 5, 2017已经结束 ¥1251
Simulation profile need a private tutor for ANSYS-Fluent and ICEM-CFD 8 矩阵及数学软件, Verilog / VHDL, 有限元分析, FPGA, 计算机图形辅助三维交互式应用 Oct 5, 2017 Oct 5, 2017已经结束 ¥1067
VHDL circuits project have few questions on digital circuits that I need help with. will provide more details of interested 23 Verilog / VHDL, 电路设计, 编程 Oct 4, 2017 Oct 4, 2017已经结束 ¥508
ROS Robot with SLAM that goes from table to table At European Innovation Academy we need a robot that goes from table to table and talks to people. Preferably the robot would also recognize people. 10 PHP, Verilog / VHDL, PLC 与 SCADA, 机器人技术, FPGA Oct 4, 2017 Oct 4, 2017已经结束 ¥34741
Voice Detection By Matlab expecrt in : MFCC CPP SVM Pre-processing data Using Matlab, we have a ready database to work with 16 矩阵及数学软件, Verilog / VHDL, CUDA, C++编程, FPGA Oct 4, 2017 Oct 4, 2017已经结束 ¥132
assembles with technical projects Future technologies will allow the integration of hundreds of billions of transistors on a single chip allowing the fabrication of chips with hundreds of processing cores. So, IC designers should focus on the communication between these cores in order to meet the design requirements in terms of speed, area, power consumption, and time to market constraints. Using conventional parallel buses to tra... 2 C 编程, 电子, Verilog / VHDL, 嵌入式软件, Very-large-scale integration (VLSI) Oct 4, 2017 Oct 4, 2017已经结束 ¥2826
Pixhawk IMU navigation system Hi Bro I need to build a inertial navigation system using a pixhawk for a drone, i have done some work on it. Do you like to help me out? i can share all the details if you are interested. thanks! 2 Verilog / VHDL, 算法, 印制板布局, , 机器人技术, 印度尼西亚语 Oct 3, 2017 Oct 3, 2017已经结束 ¥344
Matlab 2D Images I would like to generate B-Scan image from several A-Scan Images in Matlab / .NET. Will provide all necessary files if interested. 10 矩阵及数学软件, Verilog / VHDL, 算法, LabVIEW, FPGA Oct 3, 2017 Oct 3, 2017已经结束 ¥1118
MIPS Programming Simple MIPS programme. Requires little nowledge in C++ and C 12 Verilog / VHDL, 序言, C++编程, FPGA, 编程 Oct 2, 2017 Oct 2, 2017已经结束 ¥185
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