Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 雇佣Verilog / VHDL Designers

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    8 搜到的工作,价格货币为 USD
    Looking for FPGA expert 6 天 left
    已验证

    I am looking for someone having expertise in FPGA, i am looking for someone for long term work relation. People having good experience in FPGA but new to this platform are most welcomed. i will explain the details of task in chat

    $25 (Avg Bid)
    $25 平均报价
    4 个竞标
    JavaFX UI development 6 天 left
    已验证

    6 Stop Round Table (Rotating at 60 degrees) SERVO 1 is connected to rotary table. Rotary table will rotate and stop at 60 degrees. Once it stops A, B,C, D, E & F as given below will be actioned. (A) Filling Quantity User can select the pre-set quantity shown in screen (B) ALIGNMENT: (Sensor, Stepper Motor) • Sensor to detect colour code. • Stepper motor will rotate and stop when c...

    $329 (Avg Bid)
    $329 平均报价
    12 个竞标

    A reliability enhanced video storage architecture in hybrid SLC/MLC NAND flash memory

    $30 (Avg Bid)
    $30 平均报价
    1 个竞标

    Re programming plc in ladder Short contract or freelance PLC & SCADA

    $31 / hr (Avg Bid)
    $31 / hr 平均报价
    38 个竞标

    6 Stop Round Table (Rotating at 60 degrees) SERVO 1 is connected to rotary table. Rotary table will rotate and stop at 60 degrees. Once it stops A, B,C, D, E & F as given below will be actioned. (A) Filling Quantity User can select the pre-set quantity shown in screen (B) ALIGNMENT: (Sensor, Stepper Motor) • Sensor to detect colour code. • Stepper motor will rotate and stop when c...

    $307 (Avg Bid)
    $307 平均报价
    9 个竞标
    PWM vhdl fpga 3 天 left

    Description is in attached file. Note: Text is in Bosnian language so you will need to translate it.

    $144 (Avg Bid)
    $144 平均报价
    10 个竞标

    i am looking for a expert in SystemVerilog and UVM test environment for RISC-V processor.

    $14 / hr (Avg Bid)
    $14 / hr 平均报价
    5 个竞标

    i am looking for a expert in SystemVerilog and UVM test environment for RISC-V processor.

    $6 / hr (Avg Bid)
    $6 / hr 平均报价
    1 个竞标