Verilog / VHDL 工作与竞赛

Verilog是一种用于半导体和电子设计领域的描述语言,也常用于模拟和模数混合电路中。VHDL则是一种用于电子设计自动化和集成电路的硬件描述语言。如果您的业务涉及Verilog / VHDL,您可以雇佣一些自由职业者完成部分作业。现在就发布您的Verilog/VHDL项目需求,与中意的自由职业者取得联系吧。
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项目/竞赛 描述 竞标数/参赛作品数 技能 已开始 结束 价格(CNY)
Mpi Programming Mpi Programming in simple way. 6 C 编程, Java, Verilog / VHDL, C++编程, 汇编 Feb 24, 2018 今天6天 7时 ¥158
Implement RSA algorithm synthesized code (512 bit) in Verilog Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly cont... 4 工程, Verilog / VHDL, FPGA Feb 24, 2018 Feb 24, 20185天 23时 ¥1248
Design a Circuit Board *** Need expert in Kicad software****... i have attached all details of work in the word file take a look at this and let me know if you can do this work 3 电子, Verilog / VHDL, 电機工程, 印制板布局, 电路设计 Feb 24, 2018 Feb 24, 20185天 21时 ¥602
Help Business Looking forward someone who can help me Please don't hesitate contact me if you are interested Thanks 7 Verilog / VHDL, 市场, 商务, 商务智能 Feb 23, 2018 Feb 23, 20185天 19时 ¥2630
Build a simulink model of the DC motor Build a simulink model of the DC motor 19 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Feb 22, 2018 Feb 22, 20184天 17时 ¥285
Build me a computer architecture project Will need to implement parallel programming including CUDA in C++. Details to follow if anyone takes up the challenge. Hardware details to be taken care by our team. 9 C 编程, Java, Verilog / VHDL, 软件构架, C++编程 Feb 22, 2018 Feb 22, 20184天 16时 ¥1179
QPSK FPGA Demodulator xilinx (Source code required) We need to develop a QPSK demodulator FPGA xilinx based. 13 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 22, 2018 Feb 22, 20184天 6时 ¥4615
DDR3 memory controller interface using nexys video for read write multiple images We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board. 4 C 编程, Verilog / VHDL, 微控制器, 嵌入式软件, FPGA Feb 21, 2018 Feb 21, 20183天 2时 ¥957
2x2 multiplier using karatsuba algorithm implementation of 2x2 multiplier using karatsuba algorithm 11 Java, 矩阵及数学软件, Verilog / VHDL, 算法, C++编程 Feb 21, 2018 Feb 21, 20182天 23时 ¥161
SystemVerilog - Complete Single-Cycle Processor + Synthesis I need help completing a Single Cycle RISC-V datapath and control using System Verilog. What I need: - A report including how different instructions have be to implemented. The document contains all the necessary modifications in the datapath to add all the instructions. - Modify the code to implement all the instructions. 6 工程, 电子, Verilog / VHDL, 电機工程 Feb 20, 2018 Feb 20, 20182天 ¥406
DDR3 Memory controller interface using nexys video board We are working on nexys video board .We are trying to access DDR3 memory using IP core in Vivado design suit [链接已删除,请登录查看] want to read and write the data into DDR3 memory and access it in nexys video board. 5 C 编程, 电子, Verilog / VHDL, 微控制器, Arduino Feb 19, 2018 Feb 19, 201821时 45分 ¥2255
Verilog Servo controller I'm looking for someone who can write me a verilog HDL code for a servo controller 7 C 编程, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 18, 2018 Feb 18, 201815时 16分 ¥177
AI Based Chip Design For video codec h.264 for face recognition in cloud and verify output on Xilinx FPGA Kit write an AI Algorithm for video codec h.264 and design Chip, after design chip of AI Based video codec h.264 you can verify out put on Xilinx FPGA Kit for face recognition in cloud iam expecting this project to finish on or before 26th feb2018 regards D RAMANNA [Removed by Freelancer.com Admin for offsiting - please see Section 13 of our Terms and Conditions] BANGALORE-INDIA 4 平面设计, 徽标设计, 电子, Verilog / VHDL, 电機工程 Feb 18, 2018 Feb 18, 20189时 5分 ¥1045
need help with mplab project please give me full code for this project. using MPLAB software and production must be successful. make the PCB design. 5 电子, Verilog / VHDL, 微控制器, 电機工程, 印制板布局 Feb 17, 2018 Feb 17, 2018已经结束 ¥231
Electronic Engineer We require an electronic engineer who is skilled in: FPGA Programming (VHDL) PicoBlaze embedded processor (Assembler) DWIN Technology TouchScreen 7 C 编程, 电子, Verilog / VHDL, 微控制器, 电機工程 Feb 16, 2018 Feb 16, 2018已经结束 ¥195
FPGA Based NMR Spectrometer design Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details. 10 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 16, 2018 Feb 16, 2018已经结束 ¥50337
Design an analog to digital convereter Aim is to design a successive approximation register based analog to digital converter using cadence tool (any vlsi back end tool) 10 工程, 电子, Verilog / VHDL, 微控制器, 电機工程 Feb 16, 2018 Feb 16, 2018已经结束 ¥6352
adc ltc2308 in vhdl altera deo nano soc cyclone 5 board It is a basic project but since I've never worked with on FPGA before, I think someone with experience is a wise choice. The project is basically read the ADC signal from onboard adc ltc2308 and send it to the DAC. While ADC (ltc2308 ) is 12bit 7 电子, Verilog / VHDL, 微控制器, 电機工程, 电路设计 Feb 12, 2018 Feb 12, 2018已经结束 ¥513
need someone for FPGA work I would like someone to help me build a simple FPGA Kernel for a certain gaming system. I would like your help to improve a FPGA project we are using Altera Quartus programming software i have attached a QAR file First of all, compile it to a POF file and then send it to me and let me examine it and I will give you more instructions on how to proceed. It's not very complicated Let me ask... 9 C 编程, 电子, Verilog / VHDL, 微控制器, FPGA Feb 12, 2018 Feb 12, 2018已经结束 ¥975
An expert in FPGA is required I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 4 C 编程, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 12, 2018 Feb 12, 2018已经结束 ¥946
FPGA QAR Project I have a QAR file that I cannot compile into a POF or PLD file, I would like someone with experience in FPGA to do it. It must be someone with real good knowledge of FPGA. 14 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Feb 12, 2018 Feb 12, 2018已经结束 ¥3119
Help with plptools needed need perfect work Help with plptools needed need perfect work.. All the details would be given on the chat... Need to submit it till midnight today... 2 矩阵及数学软件, Verilog / VHDL, 微控制器, 数学, , 汇编 Feb 11, 2018 Feb 11, 2018已经结束 ¥475
FPGA work .... I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 5 C 编程, 电子, Verilog / VHDL, 微控制器, FPGA Feb 11, 2018 Feb 11, 2018已经结束 ¥171
FPGA CONSOLE I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 5 C 编程, 电子, Verilog / VHDL, 微控制器, FPGA Feb 11, 2018 Feb 11, 2018已经结束 ¥129
OFDM/256QAM Modulation/Demodulation and Forward Error Correction in Matlab/Xilinx FPGA IP We are looking for develop and implement OFDM / 16QAM, 32QAM, 64QAM , 256QAM Modulation / Demodulation algorithm with Matlab and implement it on Xilinx Zynq FPGA . 1- BW : tunable upto 40Mhz . 2- FEC : LDPC or Reed solomon . 11 工程, 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW Feb 9, 2018 Feb 9, 2018已经结束 ¥16671
Use edaplayground to run a carry lookahead adder need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works 11 C 编程, Verilog / VHDL, 微控制器, 软件构架, FPGA Feb 8, 2018 Feb 8, 2018已经结束 ¥152
Controller (Microprocessor Based) Design for Transport Refrigeration System Design , Prototyping of Controller (Microprocessor Based) Design for Transport Refrigeration System to control a system powered by diesel engine based power train and comprising of a Vapour Compression Cycle Refrigeration System comprising of Refrigeration Compressors , Condensors ,Evaporators , heaters etc 7 电子, Verilog / VHDL, 电機工程, 印制板布局, 电路设计 Feb 8, 2018 Feb 8, 2018已经结束 ¥4263
Steganography - open to bidding I need a C# based Desktop Applications With Following Modules The Encryption Module 1. Registration: - To access the core system, user first need to register themselves by providing required details. 2. Login: - After registration, user may login into the system. 3. Algorithm Selection: - Here, user will select the algorithm such as DES (Data Encryption Standard), AES (Advance Encryption Standa... 7 矩阵及数学软件, Verilog / VHDL, 算法, 印制板布局, 机器学习 Feb 7, 2018 Feb 7, 2018已经结束 ¥1698
CONFIGURATION OF ADS 5263 EVM WITH ZC702 OR KC705. i have ADS5263 EVM board, and i connected that board with xilinx zc702 via ADC FMC adapter. i tried to write code for that i failed to generate bit stream based on xilinx application note xapp524. i need help to sort out the problem of clock multi region routing. 5 Verilog / VHDL Feb 6, 2018 Feb 6, 2018已经结束 ¥953
integration wsn with clouds using cooja i want a specialist in cloud integration with wsn and have experience in cooja. 9 Java, 工程, 矩阵及数学软件, Verilog / VHDL, C++编程 Feb 6, 2018 Feb 6, 2018已经结束 ¥646
FIR Filter Reference Design in Verilog We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers 5 Verilog / VHDL, FPGA Feb 4, 2018 Feb 4, 2018已经结束 ¥1395
Simple MIPS interpretor Want someone to finish a MIPS project. The project will be required to be finished by the end of the day 8 C 编程, Verilog / VHDL, 软件构架, 汇编, x86/x64 汇编 Feb 4, 2018 Feb 4, 2018已经结束 ¥329
Recursive karatsuba multiplier (16bit) I need a verilog code for recursive karatsuba multiplier for 16bit signed integers. 6 Verilog / VHDL, 数字设计 Feb 2, 2018 Feb 2, 2018已经结束 ¥1234
Pthread and OpenMP I have some simple code that I want to compare in OpenMP and pThread to see which is more performant. 1 C 编程, Java, Verilog / VHDL, C++编程, 汇编 Jan 31, 2018 Jan 31, 2018已经结束 ¥222
dead reckoning Indoor positioning system we want to develop an indoor positioning system using pedestrian dead reckoning method. we are using STM32F469NI microcontroller. using only accelerometer and gyroscope. we have successfully collected the data for accelerometer and gyroscope. so is it possible to employ these data in embedded platform (keil u-vission) to develop the system. other possibility is to save the data in SD card and use ... 15 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW, Arduino Jan 30, 2018 Jan 30, 2018已经结束 ¥1248
Petalinux on ZC706 I am looking for someone who has done work on Petalinux on ZC706 or Zedboard. The person MUST have done projects of Ethernet, PS Ram usage, external permanent memory storage using PCIe based drive, SPI control. I need to develop a project using above features. 1 Verilog / VHDL, FPGA Jan 29, 2018 Jan 29, 2018已经结束 ¥1052
ddr sdram controller i want to do some modification to controller i.e either adding a module to it or pipeling it. 3 Verilog / VHDL Jan 20, 2018 Jan 20, 2018已经结束 ¥1426
build a mips recursive quicksort use recursive way to write quicksort in mips, the c code will be offered 9 C 编程, Verilog / VHDL, C++编程, 汇编, x86/x64 汇编 Jan 17, 2018 Jan 17, 2018已经结束 ¥260
Matlab Simulation-Impulse Voltage generation Need to modify a schematic(.mdl) to get desired results. The .mdl schematic is attached [链接已删除,请登录查看] need to modify the design to get proper output like Figure 4 12 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Jan 10, 2018 Jan 10, 2018已经结束 ¥268
need a VHDL expert asap vhdl expert needed asap to run a code 16 工程, 电子, Verilog / VHDL, 电機工程, FPGA Jan 10, 2018 Jan 10, 2018已经结束 ¥125
License Plate Detection Using VHDL I'm building a license plate detection system, and concept has been proven using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code 8 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Jan 9, 2018 Jan 9, 2018已经结束 ¥3618
Edge detection on Altera DE2-115 Hello, i want to create project using altera DE2-115 board to detect edges on 3 image using sobel filter and show they ober VGA 640x480. To choose which image should be apear is needed 2 swtich. i have done some algorithm with matlab and now i have to implement it on altera. Thanks 16 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, LabVIEW Jan 6, 2018 Jan 6, 2018已经结束 ¥4082
This task need to be developed using MATLAB....A cicuit bsed on fuzzy logic to detect different kind of faults L-G,L-L,LLL etc. Fuzzy logic based fault detection 9 工程, 矩阵及数学软件, Verilog / VHDL, 算法, 电機工程 Jan 6, 2018 Jan 6, 2018已经结束 ¥222
SFP communication with FPGA Coding required for FPGA to SFP communication 13 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Jan 6, 2018 Jan 6, 2018已经结束 ¥5684
VHDL for programming FPGA board Hi, I run a small sales business in the video game industry. I am looking for someone with VHDL experience to assign pins on an FPGA board for an old video game system, to a new pre-designed break out board to allow the system to use HDMI. Please contact for details. 18 Verilog / VHDL, FPGA Jan 2, 2018 Jan 2, 2018已经结束 ¥805
FPGA Design in VHDL Design of FPGA to serve as a memory mapped resource for a local processor module. The processor interface is a memory mapped address/data bus. The FPGA design contains registers, counters and data path functions. System clock frequency is 25MHz. No internal processor is used within the FPGA. An external SRAM is required for expanded data storage. The target FPGA is the Microsemi ProASIC3E. 10 Verilog / VHDL, 设计 Jan 2, 2018 Jan 2, 2018已经结束 ¥43329
Project for Varun V. Hi Varun V., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 1 C 编程, Linux, Verilog / VHDL, 嵌入式软件, Jan 1, 2018 Jan 1, 2018已经结束 ¥1584
Work with Digital Electronic and Analogue... Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 11 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 28, 2017 Dec 28, 2017已经结束 ¥165
Work with Digital Electronic and Analogue. Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 11 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 28, 2017 Dec 28, 2017已经结束 ¥215
Work with Digital Electronic and Analogue Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 13 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Dec 28, 2017 Dec 28, 2017已经结束 ¥209
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