Verilog / VHDL 工作与竞赛

Verilog是一种用于半导体和电子设计领域的描述语言,也常用于模拟和模数混合电路中。VHDL则是一种用于电子设计自动化和集成电路的硬件描述语言。如果您的业务涉及Verilog / VHDL,您可以雇佣一些自由职业者完成部分作业。现在就发布您的Verilog/VHDL项目需求,与中意的自由职业者取得联系吧。
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项目/竞赛 描述 竞标数/参赛作品数 技能 已开始 结束 价格(CNY)
Simple Verilog code Write a simple verilog code to create dynamic lighting using led. see the attached files and respond 18 C 编程, Verilog / VHDL, 微控制器, LabVIEW, FPGA Dec 15, 2017 今天6天 3时 ¥853
help me with modify some Verilog code know Verilog code, how how to use Quartus and FPGA board. 10 Verilog / VHDL, 微控制器, 电機工程, LabVIEW, FPGA Dec 15, 2017 Dec 15, 20175天 17时 ¥159
Program a microcontroller need you to program a micro controller as per my requirement 15 电子, Verilog / VHDL, 微控制器, 电機工程, Arduino Dec 14, 2017 Dec 14, 20175天 4时 ¥147
Project for Loi L. Hi Loi L., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 2 电子, Verilog / VHDL, 电機工程, , 数字设计, 电路设计 Dec 14, 2017 Dec 14, 20177天 21时 ¥694
Implement a 16-bit CORDIC Computer It is to Implement a 16-bit CORDIC Computer. The design to be implemented is based on a bit-serial configuration. It will take as input a 16-bit signed binary fixed point number, corresponding to an angle in the range 0 to Ï€/2, and use the CORDIC method to find the sine and cosine of this angle. This will be coded in Verilog and implemented on the Basis 3 board. 3 Verilog / VHDL Dec 14, 2017 Dec 14, 20174天 16时 ¥1124
Simulink design of maximum power point algorithm with DC-DC Converter I want to hire a person which having the knowledge of matlab and simulink, and design the mppt algorithm associated with my idea. Also the person should have the knowledge of electrical like DC-DC converter, basic concept of solar cell, maximum power point algorithm. 21 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 14, 2017 Dec 14, 20174天 15时 ¥926
Multiprocessor Scheduling in c++ -- 2 - 13/12/2017 14:32 EST -- 2 Inroduction: This project is about designing and simulating a clock-driven quad-processor scheduler in an object-oriented manner. The scheduler consists of a multi-level job queue where each level follows a different scheduling algorithm viz. Priority, Shortest Job First (SJF) and First-come-first-serve (FCFS). These queues will be enqueued with PCBs. The PCBs can further be classified into Rec... 4 C 编程, 电子, Verilog / VHDL, 微控制器, 电機工程 Dec 13, 2017 Dec 13, 20174天 5时 ¥145
communication using simulink blocks update file of one user to five user 9 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 12, 2017 Dec 12, 20173天 8时 ¥820
robust control project design a control system using matlab or simulink 14 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 12, 2017 Dec 12, 20173天 3时 ¥309
model in simulink i have model for one user i want update to 5 user and get some results 10 工程, 矩阵及数学软件, Verilog / VHDL, 机械工程, 电機工程 Dec 12, 2017 Dec 12, 20173天 2时 ¥2479
calculate speed between two points in verilog im making missile command and i have (x1,y1) and (x2,y2). how can I calculate the x step and y step values? 8 Verilog / VHDL Dec 12, 2017 Dec 12, 20172天 18时 ¥225
little project about emitter follower (manually and simulated) -- 2 - 11/12/2017 21:32 EST Help me to design the circuit attatched and find out the unkown parameters both 20 工程, 电子, Verilog / VHDL, 微控制器, 电機工程 Dec 11, 2017 Dec 11, 20172天 12时 ¥218
Analogue & Digital Electronic Please, see the attached file. Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 18 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 11, 2017 Dec 11, 20172天 7时 ¥1345
multisim function generator hi i want someone to connect the function generator and the scope in multisim of electric circuit thank you 9 工程, 电子, Verilog / VHDL, 电機工程, 电路设计 Dec 11, 2017 Dec 11, 20172天 6时 ¥152
Simulink to VHDL I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time. 5 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Dec 11, 2017 Dec 11, 20172天 ¥152
Microprocessor Project using CodeWarrior Software Hi, Need the completed project in 36 hours. Share the codes in 24 hours and the report in 36 hours. Project details are attached here. Sample codes are attached in the files. You need to use the similar codes for the work 3 工程, 电子, Verilog / VHDL, 微控制器, 电機工程 Dec 11, 2017 Dec 11, 20171天 17时 ¥661
VHDL to Verilog Translation I have .vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to have the same functionality with Verilog description language. 9 Verilog / VHDL Dec 10, 2017 Dec 10, 20171天 12时 ¥793
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 工程, 电子, Verilog / VHDL, 电機工程, FPGA Dec 9, 2017 Dec 9, 2017已经结束 ¥364
simulation/ VHDL Expert Needed -- Urgent job -- 3 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 3 工程, 电子, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 2017已经结束 ¥300
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 工程, 电子, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 2017已经结束 ¥233
simulation/ VHDL Expert Needed -- Urgent job -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 工程, 电子, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 2017已经结束 ¥233
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 工程, 电子, Verilog / VHDL, 电機工程, FPGA Dec 9, 2017 Dec 9, 2017已经结束 -
simulation/ VHDL Expert Needed -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 4 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 2017已经结束 ¥223
simulation/ VHDL Expert Needed I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 9, 2017 Dec 9, 2017已经结束 ¥253
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 11 电子, Verilog / VHDL, 微控制器, 电機工程, FPGA Dec 8, 2017 Dec 8, 2017已经结束 ¥2955
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 矩阵及数学软件, Verilog / VHDL, 电機工程, FPGA Dec 7, 2017 Dec 7, 2017已经结束 ¥5195
Digital Logic Circuit using Logisim Hello, I am looking to build a circuit in Logisim that requires digital logic expertise. Project description will be provided upon contact. Computer science backgrounds, circuit design, and digital logic expertise required (preferably using Logisim). 21 工程, 电子, Verilog / VHDL, 电機工程, 数字设计 Dec 6, 2017 Dec 6, 2017已经结束 ¥575
need help with missile command game on de2-115 does anyone experienced with verilog have de2-115 I need help displaying a sprite on the screen. I have all the files. 4 Verilog / VHDL Dec 5, 2017 Dec 5, 2017已经结束 ¥840
micro controller need somebody good in micro controller and has ever coded using vhdl 18 C 编程, Verilog / VHDL, 微控制器, 电機工程, FPGA Dec 5, 2017 Dec 5, 2017已经结束 ¥1150
Expert in Xilinx (VHDL-BASED) An efficient Glitch power reduction using sequential clock gating in VLSI circuits 8 Verilog / VHDL Dec 5, 2017 Dec 5, 2017已经结束 ¥1071
Project for SqUa11 -- 2 3x3 Systolic array matrix using rom and ram 2 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程, Dec 4, 2017 Dec 4, 2017已经结束 ¥79
Embedded systems Develop a minimal system that contains a PC, a microprocessor board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Once (and only after) the FPGA board is awakened, it waits for a push button action. After the button is pushed, it sends an 8-bit value in bit-serial to the... 9 电子, Verilog / VHDL, 微控制器, 软件构架, Arduino Dec 4, 2017 Dec 4, 2017已经结束 ¥278
Implementation of 32-bit MIPS Processor I need someone who knows MIPS Assembly Language and knows how to use the LogicWorks software to design a Single-cycle processor (see Figure 1 in attached document) and a Five-stage pipelined processor (see Figure 2 in attached document). Please keep all bids within the budget, otherwise you will not be selected for the project. 7 C 编程, Verilog / VHDL, 软件构架, 汇编, x86/x64 汇编 Dec 4, 2017 Dec 4, 2017已经结束 ¥773
Write an article about UVM (universal verification methodology) Dear ASIC Verification Experts, I am looking for ghost writer who is from ASIC verification background. I want a unique article which tries to explain why we need to use UVM. The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? " The article needed to be original and meaningful content. Please bid with your experience in ASIC ver... 26 Verilog / VHDL, 技术写作 Dec 4, 2017 Dec 4, 2017已经结束 ¥648
putty language i need someone who can do putty and verilog 7 工程, Verilog / VHDL, 电機工程, 汇编 Dec 4, 2017 Dec 4, 2017已经结束 ¥734
Verilog Work I need some work done in verilog using Quartus 2 version 13 12 Verilog / VHDL Dec 3, 2017 Dec 3, 2017已经结束 ¥959
putty coding language need an electrical engineer or computer engineer with background in putty language coding 3 Verilog / VHDL, 电機工程, 编程, 编程 Dec 3, 2017 Dec 3, 2017已经结束 ¥185
Need a Cadence design to design a amplifier circuit. Need a Cadence design to design a amplifier circuit. details will be share in chat box. 21 工程, 电子, Verilog / VHDL, 电機工程, 电路设计 Dec 3, 2017 Dec 3, 2017已经结束 ¥165
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 工程, 电子, Verilog / VHDL, 电路设计, FPGA Dec 2, 2017 Dec 2, 2017已经结束 ¥297
MATLAB code- a bit-serial CORDIC computer in Verilog MATLAB code a bit-serial CORDIC computer in Verilog to compute the sine and cosine of an angle θ. I will share the additional details later 15 矩阵及数学软件, Verilog / VHDL Dec 2, 2017 Dec 2, 2017已经结束 ¥410
Digital Design with Logic Devices It is a Project on Digital Design with Programmable Logic Devices. I will provide details later. 10 Verilog / VHDL Dec 1, 2017 Dec 1, 2017已经结束 ¥344
pls help ac homewokr :'( i need log synchronous sequential circuit that solves a 64x64 maze using the right wall follower algorithm. how much???? u have 3 hours 8 工程, 电子, 矩阵及数学软件, Verilog / VHDL, 电機工程 Dec 1, 2017 Dec 1, 2017已经结束 ¥549
Project for Gabriel G. Hi Gabriel! I'm working on my capsim simulation final and I got myself into a lot of debt and don't know how to fix it . I need a 70% on this and was wondering if you'd be able to help. Im currently on the 3rd round of 4. Would you be able to help me out? You were suggested by a classmate and was wondering if you'd be able to help me even though I already am on round 3. Thank... 2 项目管理, 电话销售, Excel, 矩阵及数学软件, Verilog / VHDL, Dec 1, 2017 Dec 1, 2017已经结束 ¥972
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 C 编程, Verilog / VHDL, C++编程, 汇编, FPGA Nov 30, 2017 Nov 30, 2017已经结束 ¥1038
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog / VHDL, FPGA Nov 29, 2017 Nov 29, 2017已经结束 ¥549
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 C 编程, 工程, Verilog / VHDL, FPGA, 并行处理 Nov 29, 2017 Nov 29, 2017已经结束 ¥1137
logic analyiser and waveform viewer The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single-level triggering. Only 8 bits of precision will be used for the analog channel. •Phase 1: Develop a minimal system that contains a PC, a microproce... 6 电子, Verilog / VHDL, 微控制器, 软件构架, Arduino Nov 27, 2017 Nov 27, 2017已经结束 ¥2129
interface hardware module with amber processor -- 2 - 27/11/2017 11:51 EST to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 27, 2017 Nov 27, 2017已经结束 ¥1395
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 工程, Verilog / VHDL, 电機工程, 网络管理, FPGA Nov 26, 2017 Nov 26, 2017已经结束 ¥4462
C++ based project - open to bidding cpp dependencies sorting out, we will provide you the structured file and the source code and you have to compile and run after sorting mugs from that 16 电子, Verilog / VHDL, C++编程, Arduino, 实时操作系统 Nov 25, 2017 Nov 25, 2017已经结束 ¥714
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