Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 雇佣Verilog / VHDL Designers

筛选

我最近的搜索
筛选项:
预算
类型
项技能
语言
    工作状态
    16 搜到的工作,价格货币为 USD
    Vivado HLS Expert 6 天 left
    已验证

    I am willing to pay for only Vivado HLS expert. Will discuss via interview.

    $1400 (Avg Bid)
    $1400 平均报价
    6 个竞标

    The project requires hardware & software design, implementation and testing of a simple & basic multi-function digital clock using Zynq 7000 ZED board. See attached for further information and specifications.

    $458 (Avg Bid)
    $458 平均报价
    9 个竞标

    i need to build a Gaussian elimination by MIPS

    $55 (Avg Bid)
    $55 平均报价
    12 个竞标

    create a web api connect to the fpga cyclone v (altera de10-standred) , then altera can response to hte request change connect some point with each other.

    $545 (Avg Bid)
    $545 平均报价
    4 个竞标

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
    $104 平均报价
    4 个竞标

    -Tools : Altera Quartus ,Modelsim and FPGA. -Programming Language : Verilog HDL. -This project is divided to two parts:- Part 1. Design and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 3...

    $123 (Avg Bid)
    $123 平均报价
    10 个竞标

    General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Ba...

    $50 (Avg Bid)
    $50 平均报价
    8 个竞标

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[登录来查看链接] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

    $153 (Avg Bid)
    $153 平均报价
    2 个竞标

    Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    $753 (Avg Bid)
    $753 平均报价
    1 个竞标

    Looking for automation and PLC programmer to control and program motor cycles with PLC for user input on speed and time. Have not picked out which PLC but looking into something like AutomationDirect.

    $2097 (Avg Bid)
    $2097 平均报价
    16 个竞标

    Hello, I made a code that creates an interface between the MSP430 and a 128x32 OLED, all the code is perfectly functional. I need help loading fonts with different sizes (small, medium , large). Requirements for assigning this project: Have MSP430 or MSP432; Have an OLED display;

    $25 (Avg Bid)
    $25 平均报价
    2 个竞标

    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit should be initialized with a high-active rese...

    $44 (Avg Bid)
    $44 平均报价
    10 个竞标

    Digital Circuit will be represented and simulated via ModelSim simulator. Consider the digital circuit represented below. Two eight-bit wide data input ports are added. The result is then used to set one of eight output lines according to predefined thresholds. Code this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the...

    $28 (Avg Bid)
    $28 平均报价
    11 个竞标

    Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    $565 (Avg Bid)
    $565 平均报价
    1 个竞标

    I want to find someone to simulate the code for my project in NS2.34.

    $110 (Avg Bid)
    $110 平均报价
    1 个竞标

    Hi, I need a quick prototype of an Artix-7 fpga that makes a pcie to sd card controller (SD host controller/SD bus). Objective is to have a fpga card (working on pcie screamer) recognized as a SD/MMC card reader under windows, I need Windows to recognize/be able to install the windows built-in sd card drivers for the card. I don’t need it to actually read sd cards, I just need to simulate...

    $252 (Avg Bid)
    $252 平均报价
    3 个竞标