Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. 雇佣Verilog / VHDL Designers

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    16 搜到的工作,价格货币为 USD

    DESIGN OF NAND MEMORY CONTROLLER ARCHITECTURE FOR BIG DATA STORAGE

    $30 - $250
    $30 - $250
    0 个竞标

    I am looking for an engineer who has good knowledge of Codesys for Programmable Logic Controllers (PLC). The freelancer must have experience of doing technical writing as well. More details will be shared with the shortlisted freelancer.

    $176 (Avg Bid)
    $176 平均报价
    3 个竞标
    VHDL Verilog 5 天 left
    已验证

    Kann mir jemand helfen dieses Verilog Problem zu lösen?

    $38 (Avg Bid)
    $38 平均报价
    2 个竞标

    Hello Everyone I am looking for an Engineer with sound knowledge of CODESYS for completion of project. More details will be shared with experienced and interested freelancers. The person must have sound knowledge of technical writing as well to handle the description part of the project. Kindly place your competitive bids for further discussion.

    $92 (Avg Bid)
    $92 平均报价
    9 个竞标

    Project Description: 2-Stage Project with 2 milestone payments. 1. The 1st stage is completion of the board design (must use Orcad/Cadence software), which includes schematic, printed circuit board and Bills Of Materials. 1st milestone payment on successful completion of 1st stage 2. The 2nd stage is coding the software with good documentation and 2nd milestone payment is made on successful c...

    $588 (Avg Bid)
    $588 平均报价
    45 个竞标

    I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.

    $3823 (Avg Bid)
    $3823 平均报价
    17 个竞标
    ADC in FPGA 2 天 left
    已验证

    Implementation of suitable RC filter for ADC. Digital part implementation is done on FPGA. RC filter has to be designed for given specification.

    $22 (Avg Bid)
    $22 平均报价
    8 个竞标

    VHDL code of optimization algorithm fixing.

    $59 (Avg Bid)
    $59 平均报价
    9 个竞标

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $167 (Avg Bid)
    $167 平均报价
    3 个竞标

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $27 (Avg Bid)
    $27 平均报价
    2 个竞标

    i want to design step by step antenna by CST program (spiral antenna) by TeamViewer you will describe to me how to design it

    $120 (Avg Bid)
    $120 平均报价
    13 个竞标

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $169 (Avg Bid)
    $169 平均报价
    3 个竞标

    Hello Please check it carefully. /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ......................................................... [登录来查看链接] have a look here, at the moment I need only labaa 3. maybe you have to download the files because on drive, ...

    $23 (Avg Bid)
    $23 平均报价
    2 个竞标

    DVLSI project 'ASIC design of face detection using haar wavelet'. Use verilog, FPGA and Viola Jones algorithm

    $298 (Avg Bid)
    $298 平均报价
    2 个竞标
    Operating System Computer Engineer 5 小时 left
    已验证

    need an operation system engineer to help in mathematical CPU process

    $160 (Avg Bid)
    $160 平均报价
    7 个竞标