VHDL implementation of DCT/IDCT for image processing synthesizable on xilinix nexys2 spartan 3e kit.
I'd love a complete core for DCT/IDCT which an [login to view URL] file could be instantiated and initilize on block ram of FPGA (or any other suitable methods of loading the image file on FPGA). The idea is to connect an INPUT_FRAME_BUFFER RAM which loads 8x8 blocks into DCT/IDCT core and an OUTPUT_FRAME_BUFFER RAM which stores 8x8 blocks output.
Here's an idea of what I would like to implement on the FPGA hardware...
I have a 240x160 pixel data stored in a .coe file or which will be instantiated and initialized in a block ram on the fpga .
I want to load 8x8 blocks into the core and store 8x8 blocks of output, hence, the need for the input and ouput buffers.
I want to perform the operation in such a way that the 240x160 pixel data stored in the ram(buffer) will be injected into the core in blocks of 8x8, and resulting output of 8x8 blocks stored in another ram(buffer).
The idea is to inject an image into DCT and compare the resulting image coming out of the iDCT.
More details will be provided.
HI,
I work with fpga xilinx and altera.
In the past I have done the fft (or dct as you like) on altera vhdl.
I can do this for you
thank you
maurizio stefani
Hi, I have 4 years of experience in the field of VLSI Design/Verification. I am interested to do the project. Please go through my profile and message me for further considerations. Thanks.
Experienced engineer in FPGA & ASIC design with prototype boards to verify implementation (also Spartan3 boards from Digilent). I can start the work now!