Hi,
I am doing my masters in VLSI at IIT Madras India. I have been doing a lot of RTL coding in last 2 years. Since i have access to Virtex 5 FPGA from Xilinx I can test the code on FGPA before giving it to you.
Here is what i propose,
We can use the HDL coder in Matlab and optimize it further for performance.
What will be delivered:
1. RTL code
2. Simulation results in Isim
3. Snapshots of Chipscope tracking the output from FPGA
I promise to keep time in mind and work. I will in constant touch with you. This is the best price i can provide you. If interested please write to me.
Looking forward to work with you.