College Project
$100-200 USD
货到付款
Design a software that will be able to convert VHDL scheme into Prolog description.
Example:
///------VHDL----//
entity andno2 is
port (
x1, x2: in Bit;
y1: out Bit);
end andno2;
architecture StructAndNo2 of andno2 is
component and2
port(a1, a2: in Bit; b1 out Bit);
component no
port(a: in Bit; b out Bit);
begin
c1: and2
port map(x1, x2, z1);
c2: no
port map(z1, y1);
end StructAndNo2;
........
// ----//
Should be come this in Prolog:
andno2(x1, x2, y1) :- and2(x1, x2, z1),
no(z1, y1).
unit(x1, x2, x3, y1, y2) :- andno2(x1, x2, z1),
and2(x2, x3, z2),
and2(z1, z2, y1),
and2(y1, z2, y2).
## Deliverables
1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.
2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables):
a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment.
b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request.
3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement).
## Platform
Linux. C++.
项目ID: #3157669