Design of a pipelined based multiplier accumulator unit for Image processing purpose
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I am doing verilog HDL for my final year project.
My title is Design of a pipelined based MAC unit for image processing purpose.
I have the sample coding but i cant run it as it contain error. Can someone please help me on that?
This is the link for my coding.
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Thanks and please reply me soon. Its urgent
项目ID: #10189733
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有4名威客正在参与此工作的竞标,均价RM561/小时
I am working as FPGA design engineer since last 6 years. I have worked in image preocessing domain for 5 years. I have expertise in both verilog and vhdl. I can complete this job with greater accuracy.
Hi, we have many years experience working with Xilinx/Altera FPGA and Verilog/VHDL programing languages. We can surely help you solve the problem. Could you please share more details about your issue? What is your p 更多