Verilog FPGA DE2 SO1 Board GameOver & Win Screen

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I am an Electronics Engineer with a Masters Degree in Microelectronics and specializing Digital IC Design. I am very eager to do IC designs, verifications, automations, and technical research. In my previous job, I did verification and debugging of the SPI block and other digital blocks. I have also done several digital designs in Verilog and VHDL. Some of these are I2C Protocol, CRC, Count Up/Down Timer, Controllers, the digital part of the 5.8 GHz Integer-N Phase-Locked Loop Frequency Synthesizer for WiMax Receivers, etc. These are either implemented in FPGA and ASIC (65nm Technology). The most complex design I did is the Reed-Solomon(836,820) Encoder and Decoder. It is a non-binary cyclic code which can detect and correct error. The RS Encoder is composed of Linear Feedback Shift Register (LFSR) and multiplication of a specific Galois Field. Meanwhile, the RS Decoder is composed of 4 main blocks, namely: Syndrome Calculation, Chien Search, Forney's Algorithm and the Key Equation Solver (inversionless Berlekamp-Massey Algorithm). This implementation "A Fast Parallel RS Decoder in 65nm Technology" was presented in a Technical Conference.