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(BIST) Built in self test verilog/ vhdlcode for memory

The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim.

Need Simulation waveforms for the same.

技能: 工程, 微控制器, Verilog / VHDL

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( 0个评论 ) Bangalore, India

项目ID: #17806030

2 威客就此工作平均出价 ₹30000

EslamElGeddawy

Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 3+ years of experie 更多

₹30000 INR 在5天内
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2.8
kartikprmr

Hello, I have expertise in ASIC/FPGA Design & Verification and worked on following languages. VHDL Verilog Systemverilog/UVM MATLAB Python Perl EDA Tools: Modelsim/Questasim Xilinx VCS Simulink I have worked on BI 更多

₹30000 INR 在15天内
(0条评论)
0.0