Designing a testbench in verilog
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I have to write a test bench for the given module, i already have the previous testbench, just need to add few more details as attached.
项目ID： #11809135
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Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS 更多
Hello sir, I am a hardware engineer. I've done many projects on IP core using Verilog. It would be my pleasure to work on your project. Please contact me to discuss the details. Thank you for your consideration
Will you be needing assertions ? Is there a specific program you want to use ? Quartus, ModelSim, etc...?
I have the experience of implementing a full processor using verilog. I think i can do it
