bubble level project

已关闭 已发布的 6 年前 货到付款
已关闭 货到付款

the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board.

In the video attached in the .zip, the operation of the project

FPGA Verilog / VHDL

项目ID: #15762690

关于项目

5个方案 远程项目 活跃的6 年前

有5名威客正在参与此工作的竞标,均价$74/小时

sourindu

A proposal has not yet been provided

$55 USD 在4天内
(1条评论)
2.3
alexstyle

The offer is purely indicative and we could discuss the details by chat.

$35 USD 在10天内
(0条评论)
0.0
chinhtranduc

I have experience working on FPGA kits such as Xilinx Artix 7 development board, Numato NESO,.. Relevant Skills and Experience FPGA, Verilog/VHDL, image processing, C/C++ Proposed Milestones $35 USD - please add more 更多

$35USD 在1天里
(0条评论)
0.0