VHDL task-1

Dear sir I have more than 9 years experience in digital design please check my profile also please message me so that we can discuss

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

Hello, My name is Mohamed. I have 5 years experience in VHDL and Digital design. I am free to work on your project. Contact me for more details. Please. Regards

Hello, I am an electronics engineer having experience of FPGA based digital system design for more than 5 years.

Hi, I have 7+ years experience working in Hardware/Embedded System design field. I'm expert in Verilog/VHDL and familiar with Xilinx/Altera FPGAs as well as their tools. I can surely help you. Could you please describe your problem?

I am good in VHDL coding. Designed I2C, MDIO, SPI, wishbone and many other controller in VHDL. Implemented AES encryption on ethernet packets in xilinx FPGA. Worked in Quartus 13.0.2 for Max-V, 10 and Cyclone-V. Implemented real-time in system programing(ISP) and ISP clamp like features. Please elaborate me your requirement, if solvable, I will definitely solve it in minimal logic and time.

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Hi, i am experimented in VHDL design/simulation and i worked on many projects using quartus tool. I’m very excited to help you in making your project successful.