design and implementation of 32bit risc processor

**Objective **[login to view URL] of the 32-bit RISC Processor Specifications . [login to view URL] Design from RISC processor specifications. [login to view URL] /RTL modeling of Design blocks. [login to view URL] of stimulus modules to test the functionality of Design Blocks. [login to view URL] design to extract Gate level net list. **RISC Processor **The RISC? must use simple constructs and have small instruction set compared to CISC? Processors.? The striking feature of RISC is that, it executes each instruction within one clock cycle. This is achieved carrying out most of the operation with in the Processor and minimizing the use of frequent operations requiring slower peripherals. Its architecture simplifies the instruction set and encourages the optimization of register manipulation. Almost all instructions have simple Register addressing. An important aspect of the instruction set is that it is easy to decode (Fixed length instruction format). Thus the Opcode and Instruction Register fields can be accessed simultaneously. Due to the Simplification of the instructions and their format so control logic design is very much simplified.**? ** **Arithematic Logic Unit(ALU)** This project deals with the designing of a? RISC processor. It is? capable of representing real numbers. ALU ? operations are incorporated into the design as [login to view URL] logic for these is different from the ordinary arithmetic functions. The numbers in contention have to be first converted into the standard IEEE? standard representation before any sorts of operations are conducted on them.? arithmetic functions like *addition*, *subtraction, multiplication* and *division* will be implemented by the processor. Below are the various functional blocks of RISC processor [login to view URL] Counter, Instruction Register, Arithmetic Logic Unit (ALU), Register organization, Control & Decoding Unit, Memory block, 32 bit ***? Addition****, **Subtraction, Multiplication, Division, branch prediction*** ? blocks. ****The project also need to have the pipeline.? **Design, RTL Coding, Synthesis and Implementation** is done using various EDA tools. ## Deliverables i need that project as soon as possible as i need to submit to my superior ...i would like to have coding n everything related to that project..