Build a signal peak detector on FPGA

Dear sir I have more than 9 years experience in digital design using fpga please check my profile also please give me more details about the shape of the signal Best regards

i can do this task for you

A proposal has not yet been provided

I need to know more about your project. Do you filter the signal before the detector? What tools are you using to simulate the design? What tools are you using to compile the design? Can you tell me more about the project? I've done a lot of wireless design. I have done whole wireless modems for companies in America. Maybe I can do a larger portion of this design for you. This project is pretty simple.

Greetings, I have good expertise with VHDL/Verilog, DSP. I can certainly assist you on this. Please see my profile for my experience. What is the clock frequency for the FPGA ? Also you want a synthesize-able code which you can put on a FPGA and test ? Do you have any specific FPGA in mind ? Look forward to hear from you. T & R Alok Pugalia

Hello, I am an expert Verilog HDL hardware descriptor with a lot of experience developing for FPGAs. One was a 6 months project involving the Digilent Nexy3 Spartan6 FPGA development board. Do feel free to read more about it at my Freelancer.com profile, by referring to the image that shows a digital system logic with interconnections. For giving in some thoughts to the problem I have figured out and algorithm which I can implement which I believe will turn out rather efficient and general purpose. But ultimately it will be nice if there are properties which the signal is already known to satisfy. Do let me know the details so I get started on your project.

Will have to implement a rising edge detector. And count how many edges present in a fraction of second. Please provide the hardware details. if the signal is analog we may need to sample the signal with an ADC and then find out the maximum peak. Thank you.

Hello, I have 10 years experience in verilog coding and using FPGAs. I have worked on development of USB 3.0 host IP and have demonstrated several other complex projects on FPGAs. I have developed designs processing data at 9 gbps. I am very confident to complete your job efficiently. Please have a look at my profile. I will synthesize and implement design with timing closure so that you will be sure your design will work on fpga. Hope to hear from you soon.

Hello sir, i have experience in fpga design like your work. I have implemented projects to monitor 3phase signal(parameters : voltage, currents, freq and phase angle) using adc to feed data to fpga. I have hardware knowledge too for this kind of electronics. Allow me for further discussion.