Signal and Power integrity Simulation in HyperLynx tool (Onsite)

This is Dinesh KS from Synergy circuits PVT LTD. (HBR Layout -Bangalore) We required your support to do the simulations in HyperLynx software, frequency response, eye diagram, S-Parameter extraction, Insertion loss, return loss, Signal integrity etc , So needs to support from our locations We will start this project within few days, but right now we don’t have input from client side, But we required the price details from you, so I sent example input, based on that provide the Quotation. The Example circuits are attached and below mentioned details are the Example inputs from SI simulation. Input schematic: attached. Material : Metron 6 Board thickness: 180 mil Stack up: 22-26 layers. Frequency: 6GBS Clock speed: 400MHz. Total signal: 12 signals from DUT to the tester (4 signals thru a relay and 8 signals thru inductor ) and including via structure. USB0_DM0 A17 To Tester Channel relay 45ohm to gnd relay 130 ohm to gnd USB0_DP0 B17 To Tester Channel relay 45ohm to gnd relay 130 ohm to gnd USB1_DM0 C20 To Tester Channel relay 45ohm to gnd relay 130 ohm to gnd USB1_DP0 D20 To Tester Channel relay 45ohm to gnd relay 130 ohm to gnd USB0_RX0P A16 To Tester Channel Loop back USB0_TX0P via 0.1uf - series L with TC USB0_RX0M B16 To Tester Channel Loop back USB0_TX0M via 0.1uf - series L with TC USB0_TX0P A18 To Tester Channel Loop back USB0_TX0P via 0.1uf - series L with TC USB0_TX0M B18 To Tester Channel Loop back USB0_TX0M via 0.1uf - series L with TC USB1_RX0P A19 To Tester Channel Loop back USB1_TX0P via 0.1uf - series L with TC USB1_RX0M B19 To Tester Channel Loop back USB1_TX0M via 0.1uf - series L with TC USB1_TX0P B20 To Tester Channel Loop back USB1_TX0P via 0.1uf - series L with TC USB1_TX0M A20 To Tester Channel Loop back USB1_TX0M via 0.1uf - series L with TC Design: OrCAD & Allegro. Please review the inputs and provide Quote. Thanks Dinesh KS +919844615310 Design Mangaer Synergy circuits pvt ltd India