32-bit MIPS processor in VHDL

The processor I want to design is a 32-bit version of the MIPS processor, however the instruction set only needs to be a small subset of the actual MIPS ISA. It should implement the multicycle datapath version of the processor utilizing the VHDL hardware descriptive language. The processor should support three instruction formats: R-format, I-format, and J-format The memories should be word addressed where each word is 32 bits. The following instructions should be implemented : lw ,sw, add, sub, and, or, slt, j, beq, nor, bne, addi ,andi ,ori . I'd also like an explanation of how the code works and possible communication via skype (or any other VoIP/Text and not necessarily via microphone if that's an issue).