I have experience with the serial interfaces: UART, SPI and I2C. I believe I can create a Verilog testbench that functions as I2C master, with configurable read / write / clock rate. I went over your files, it looks like the I/O function is missing: I can see 3 interfacing signals: i2c_sda_o, i2c_sda_i, i2c_scl_i, but I2C has only 2 signals (SCL, SDA), so if you want to simulate external pins, I think that there should be an I/O module, especially for the SDA line, that works as input + open-drain output, or as bidirectional. Otherwise, if you want to simulate internal chip signals, then I think it's OK as it is now (under some assumptions regarding the I/O module).