Implementation of Gradient descent optimizer on FPGA in verilog code which is synthesizable

I need to design gradient descent optimizer on FPGA in verilog language and code should be synthesizable. entire design should be pipelined. Input and outputs should be in single precision floating point representation. loss or cost function is mean square error loss for 2D variables, minimise the above cost functions to achieve the optimised value. I have developed gradient descent optImizer on python , below attached file is code of it. I want same implementation in verilog