Uvm/system verilog experts verify IP

Hi, I'm a professional Design Verification Engineer and have a wide experience of UVM Verification. I have worked with various UVM VIPs and done coverage closures. I can get on to your project immediately and get it done asap. Please message me with the details. Thank You

Hello, I am a senior ASIC design and verification engineer working for more than 8.5+ years. I have hands on working experience with UVM 1.2 and have worked on setting up verification environment for Ethernet IPs on Questa/Modelsim. I hope I will be a good fit for your job. Feel free to DM me to discuss the project in detail. Thanks.

I have 1.5 year of ASIC Verification Experience. I have developed testcases(in System Verilog and UVM) for customized ethernet IP such as Long packet, short packet, Medium data length packet, etc. Please share me the details (specifications) of your IP. Also let me know that do you want only testcases to be developed? Do you have Environment ready?

hi, I am expert in SV an uvm. king let us know your requirements. ping me to understand more about problem statement

Hands on experience on IP level verification environment development using UVM and system Verilog. • Hands on experience on AMBA- AHB, APB, SPI and I2C protocols. • Hands on experience on writing coverage's. • Hands on experience on writing random test scenarios. • Hands on experience on Cadence NC-Sim, Virtuoso, Questa-Sim tools.