Add-sub unit with register file (3-ported RAM)

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3 ported register file using LPM 32 bit registers using LPM design add/sub unit usign LPM (add required flags) MIPS R-type use vhdl code to describe add/sub unit intiallize 3 ported ram using MIF file to the number used in ADD/SUB modelsim is MUST

项目 ID: 31807016

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@senthilps3

Hi I have experienced in Quartus II LPM (mega wizard IP )and VHDL, also I have the prior experience in MIPS processor and its ISA. you can verify my profile for recent projects about MIPS processor Thank you

$30 USD 在2天之内

5.0

(6条评论)

2.6

5威客以平均价$32 USD来参与此工作竞价

@tyuturkinnik

Dear Client. I am Nikita Thank you for your posting. I've just read your description and guarantee 100% success on your job. Let's discuss about budget and deadline on private chat. Looking forward to hearing from you soon. Thanks

$25 USD 在1天之内

5.0

(14条评论)

3.8

@yanatejaip5s

I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module from Verilog. Previously i was done a project with verilog and the client from Russia to make CRC with 1 bit error correction based on the algorithm that the client gave to me and i have done it <24/7. Hopefully my skill and experienced could fulfill this project's requirements. Thank You

$40 USD 在1天之内

0.0

(0条评论)

0.0

@mishkaten

Hello, I am 3+ years experienced in Verilog / VHDL. I have studied it in university where I closed this course on 100/100. I've done tons of code in University :)

$12 USD 在2天之内