I need a verilog designer for making an atm model using fsm which will be implemented on cyclone V fpga

I am verilog expert with more than 8 years of experience in designing various digital systems. I am very confident on implementing the given state machine within short span of time. Lets start the project ASAP after discussing requirements through messages.

Hello! My name is Dervis and I'm excited to tell you about my skills as a verilog designer. Specifically, I have worked on projects in the area of industrial automation, specifically in the area of wastewater treatment plants and water treatment plants automation. I have a strong understanding of the requirements for this project and can confidently say that I am the best fit for this job. With my skills in electronics, software development and hardware design, I am confident that I can deliver an ATM model using FSM that will be implemented on the Cyclone V FPGA. Additionally, I believe it is important to keep I/O utilization at a minimum so that simulation with testbench simulation, synthesis and implementation can take place without any issues. Additionally, it is preferable if the implementation of the STATES is done in different submodules so that overall flow is controlled by the Main module containing the FSM. This will ensure maximum efficiency in terms of power consumption and timing constraints as well as keeping any other specifications necessary for the model to work. If you would like to discuss further please feel free to reach out to me directly and we can discuss further!

Hello My name is Mohamed, I'm a hardware digital design engineer, I have experience in FPGA Flow and ASIC Flow. For Cyclone V , i did many projects using Quartus and implemented the design on DE0-CV FPGA. Also I'm experienced in RTL using Verilog/VHDL. Additionally , i will build a complete environment to test the design from any bugs and write a descriptive document to you. We can descuss the price for all of these. I am excited about the opportunity to work with you and contribute to the success of your project. Please feel free to reach out to me so we can discuss the project further.

Hello, I am an experienced FPGA Engineer, I have experience in RTL coding using Verilog HDL, Debugging and simulation using Modelsim, and synthesis using Vivado/Quartus. I will deliver you the RTL codes, simulation results, synthesis results, and the bitstream file if needed. Feel free to contact me if interested for more details, looking forward to working with you. Have a great day

Hi Client, I have Experince in Vlsi design and veriffication , i and my team working on diffrent projects using diffrent type of tools like xilinx,Vivado, Cadence, Modelsim ect.... I and my team working on FPGA'S like Spartan, Artix7, Basys3, Zynq, ect.... So I am sure I will help in your project,if you want more details you can freely text to me. Thank you

Can be implemented as per your requirements! verilog hdl will be used! Any banking related fsm is ideal to implement on mealy coz the output will depends on both input and as well as current state. but can also be implemented with moore logic if client wanted!

Hi, I see that you are looking for a verilog developer to design a state machine for ATM tailored for Cyclon FPGA. Owing to my extensive experience in this field, I believe I can do your project within 2 days. This will be my deliverable for your project: i. ATM fsm verilog code ii. Test bench iii. Modelsim simulation result iv. Quartus based block diagram v. Quartus based state machine fiagram vi. Quartus project so you can open project on your PC. vii. Pins assigned for Cyclon FPGA I'll be more than happy to discuss any further requirements of your project. Note: I have a 100% refund policy, If my code fails to satisfy your requirement. Best wishes Bakhtiar Raham