i need a simple reed solomon encoder and decoder (16 8) with verilog code and its simulation results
I am looking for a freelancer to help me with my project. The skills required are Design, Programming, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹1000 - ₹1200 INR. I have not provided a detailed description and have not uploaded any files.
I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.
We have a team to develop Applications using the skills MATLAB,VERILOG,VHDL and PHP
I'm looking for an UX designer who can help me get an overview of the processes that an UX designer goes through. I'm thinking of making a career change from software engineering to UX design and I really enjoy using Sketch to visualize any idea striking my mind! However, UX design is n...really enjoy using Sketch to visualize any idea striking my mind! However, UX design is not only about the visuals but mostly centered around the user so I would like to get in contact with someone who can guide me through the process of working on projects, show me some previous work for steps that must find place and moreover be there for me if I'm having any questions. I'm thinking of learning framer for prototyping as I have solid background in JS, .Net, Java and C Loo...
I am looking for a freelancer to help me with my project. The skills required are C# Programming, C++ Programming, LabVIEW and Verilog / VHDL. I am happy to pay a fixed priced and my budget is R$750 - R$2250 BRL. I have not provided a detailed description and have not uploaded any files.
Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).
Hello, I require one experienced Electronic Design Engineer to design some projects. You must have experienced in VHDL and Verilog languages. Only Experienced bidders will be accepted. Details will be given to the selected bidder. Happy Bidding
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.
I do have the block and codes.. Just need short report about it in shortest time.
I need Verilog code for fused multiply add unit for single precision floating point unit. The code needs to run on a Spartan 6 FPGA. I will run it here on Xilinx ISE.
Do you have work on TCP/IP protocol implemented on Altera FPGA and worked with internet ? it is better wrote on verilog-HDL , thanks so much
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim
I am looking for a freelancer to help me with my project. The skills required are Geology, Haskell, Lisp and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.
Do you have work on TCP/IP protocol implemented on Altera FPGA and worked with internet ? it is better wrote on verilog-HDL , thanks so much
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.
my project is about parking space , it has 8 parking avaliabe .. each park have a light .. if the light was green it means that the park is available, if it wasn't it turn to red. we want to do it in ( verilog) language and apply it on ( FPGA- board ) .. the final result should include the code and state diagram
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.
Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.
Description of analysis: Description of analysis: To collect 75nos of valid telephone numbers of the architect company data by taking the following steps: 1/ on find London architects, subject to them based or registered addresses in postcodes SW1-SW15, WC1, WC2, EC1-EC4, W1-W6, NW1, NW8, NW6, N1, E1, SE1, SE16, SE5; 2/ filter to the next list only those companies that have websites and confirm on their websites they work/design residential; 3/ go onto and filter onto the next list companies, subject to a company having minimum £10k net assets (this data is freely accessible) and paste onto the google spreadsheet made up of: 3.1/ 25nos companies which are established/registered between 2005-2008, 3.2/ 25nos companies which are established/registered between
I need a new website for my Letter Photography. I need you to design and build my online store so ppl can choose photos, place their order, pay and have the order sent to my framer. The website needs to allow customers to type in letters and numbers, then scroll through our matching photos selections. Thanks for your time. I hope you have a wonderful day.
Need a vending machine circuit, for counting coins.
necesito transmitir datos numericos entre la fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en form...fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un p...
SystemVerilog Using Quartus, and ModelSim Need to design the entire sha1 module (Design the yellow box) *There are more files that I will provide
...*** Description: Implement a hw/sw project in Parallella board (). So it is necessary that you have worked on this specific board and the source code that you deliver must be designed and must be run on this board well. the project can be one of these: 1. implement SDN gps that incorporate support for multi-constellation operability, with inclusion of Galileo E1 and GLONASS L1 signals. it should use the PS, PL and also Epiphany parts of the parallella board efficiently 2. implement AES encryption algorithm in the parallella board. it should use the PS, PL and also Epiphany parts of the parallella board efficiently and get better performance than implemented on similar platforms (like raspberry pi or other single board computers or even if it's possible
32 bit coprocessor floating point unit i have the program. only i want to remove the errors which are 12.
Details will be shared with winning bidder. I have the mulitple project. please bid.
Minimum 8bit processor verilog code for fused multiply add unit in verilog and implementing it on bysys3 using xilinx vivado 15.1
Minimum 8bit processor verilog code for fused multiply add unit in verilog and implementing it on bysys3 using xilinx vivado 15.1
The Simple Computer from Chapter 8 of the textbook is a single‐cycle, load‐store central processing unit (CPU). The singlecycle Simple Computer illustrates many of the major principles and design constraints involved in implementing a CPU. For this project, you will write a small program to process the values stored in an array in the data memor...Chapter 8 of the textbook is a single‐cycle, load‐store central processing unit (CPU). The singlecycle Simple Computer illustrates many of the major principles and design constraints involved in implementing a CPU. For this project, you will write a small program to process the values stored in an array in the data memory. You will verify the operation of your program on the Simple Computer in a Verilog simulation and on the DE0 Nano ...
Looking for framer, drywaller, mudding and taping. Full gut renovation job on Danforth
I am looking for a freelancer to help me with my project. The skills required are Arduino, FPGA, Microcontroller and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 AUD. I have not provided a detailed description and have not uploaded any files.
I am looking for a freelancer to help me with my project. The skills required are FPGA, Imaging, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.
Task is to replace all Identifiers in Verilog Source Code file: (1) Find all Identifiers in Verilog Source Code file and save them in file, one at line. For example: name1 name2 name3 ... nameX (2) Then User adds replacement in the file (old_name=new_name) name1=new1 name2=new2 name3=new3 ... nameX=newX (3) Replace Identifiers in Verilog Source Code file according to the file, name1 is replaced by new1 and so on. Identifiers are names used to give an object, such as a register or a function or a module, a name so that it can be referenced from other places in a description. * Identifiers must begin with an alphabetic character or the underscore character (a-z A-Z _ ) * Identifiers may contain alphabetic characters, numeric characters, the undersco...
I am looking for a freelancer to help me with my project. The skills required are , Matlab,simulink and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $50 - $250 AUD. I have not provided a detailed description and have not uploaded any files.
I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $30 - $100 USD. I have not provided a detailed description and have not uploaded any files.
Do you have experience in digital design? Verilog Please look at the attached file. I need to do it for group C and group F Each group independently This is not an academic project, I need this for my company.
i want to monitor power on the fpga board. its MAX 10 NEEK board from altera. The task is to monitor the voltage rails when a load is running on the board. The load will be different video signals being run on the lcd of NEEK board. HDMI in is recieving video from either HDMI player or just directly from a laptop HDMI out .could be a video played on youtube or VLC player. There is a code which displays the video on the LCD successfully. There is another example code for power monitor when there is no load running on the board. Instantiation of one needs to be done with the other.
I need to check if a post starts with certain letters like one will be checking if post title starts with e1, e2, and another to check if post starts with ne1, ne2. I have the following code, but it checks if the values are anywhere in the title, I need it to check the very start of the title, I don't have ftp/wp admin access for you - so if you can work on your own install and send on the finished code.
Hi, Only serious bidders please. Before awarding the project, I will take an interview related to Embedded System Design. Write “I am ready for interview” in your bid so that I should know that you have read my project description, else REJECTED! I need presentations (ppt) on the following: 1. Xilinx Virtex-7 FPGA 2. System Verilog 3. PIC 4. Network on Chip (NoC) 5. AVR Architecture Furthermore, I need ppt converted to pdf of 1. RISC 2. CISC 3. Power PC 4. Multicore Architectures.
Hi loi09dt1, I noticed your profile and would like to offer you my project. We can discuss any details over chat.
creation of a simplified CPU using an HDL such as Verilog. The design is a basic 32-bit RISC-style microprocessor. This will be a CPU where the basic operand format for arithmetic and logic is a typical three operand (two source, one destination) form. Primary memory access is implemented as load/store involving a single register and memory. A stack will be implemented. The general-purpose register set should be made as orthogonal as possible with special-purpose registers (e.g. program counter, stack pointer, condition flags, etc.) accessed separately.
In this project we need to write a code to scan a RGB LED matrix using a sp...show video. You have to write a code to refresh FPGA's internal frame buffer onto the connected LED panel using serial connections. To better under stand the whole thing here we have a exact project example done by someone else which explains everything about the LED panels and how it works in below link. It also has an example of verilog coding the same thing. there is another example project done with Altera FPGA code written in VHDL. You can refer both for help. second example is as below. Remember we only have to write FPGA side code not the whole thing including beaglebone stuff and all.
Hi ahmedmohamed85, I noticed your profile and would like to offer you my project. We can discuss any details over chat.
